@inproceedings{10.1007/978-3-030-01090-4_29,
    Abstract = {Reactive synthesis aims at automatic construction of systems from their behavioural specifications. The research mostly focuses on synthesis of systems dealing with Boolean signals. But real-life systems are often described using bit-vectors, integers, etc. Bit-blasting would make such systems unreadable, hit synthesis scalability, and is not possible for infinite data-domains. One step closer to real-life systems are register transducers [10]: they can store data-input into registers and later output the content of a register, but they do not directly depend on the data-input, only on its comparison with the registers. Previously [5] it was proven that synthesis of register transducers from register automata is undecidable, but there the authors considered transducers equipped with the unbounded queue of registers. First, we prove the problem becomes decidable if bound the number of registers in transducers, by reducing the problem to standard synthesis of Boolean systems. Second, we show how to use quantified temporal logic, instead of automata, for specifications.},
    Address = {Cham},
    Author = {Khalimov, Ayrat and Maderbacher, Benedikt and Bloem, Roderick},
    BookTitle = {Automated Technology for Verification and Analysis},
    Editor = {Lahiri, Shuvendu K. and Wang, Chao},
    File = {Bounded synthesis of register transducers - Khalimov2018\_Chapter\_BoundedSynthesisOfRegisterTran - a - a - c.pdf},
    ISBN = {978-3-030-01090-4},
    Pages = {494--510},
    Publisher = {Springer International Publishing},
    Title = {Bounded Synthesis of Register Transducers},
    Year = {2018},
    date-added = {2020-03-02 14:05:28 +0100},
    date-modified = {2020-03-02 14:05:28 +0100},
    doi = {10.1007/978-3-030-01090-4_29}
}

@inproceedings{10.1007/978-3-030-01090-4_29, Abstract = {Reactive synthesis aims at automatic construction of systems from their behavioural specifications. The research mostly focuses on synthesis of systems dealing with Boolean signals. But real-life systems are often described using bit-vectors, integers, etc. Bit-blasting would make such systems unreadable, hit synthesis scalability, and is not possible for infinite data-domains. One step closer to real-life systems are register transducers [10]: they can store data-input into registers and later output the content of a register, but they do not directly depend on the data-input, only on its comparison with the registers. Previously [5] it was proven that synthesis of register transducers from register automata is undecidable, but there the authors considered transducers equipped with the unbounded queue of registers. First, we prove the problem becomes decidable if bound the number of registers in transducers, by reducing the problem to standard synthesis of Boolean systems. Second, we show how to use quantified temporal logic, instead of automata, for specifications.}, Address = {Cham}, Author = {Khalimov, Ayrat and Maderbacher, Benedikt and Bloem, Roderick}, BookTitle = {Automated Technology for Verification and Analysis}, Editor = {Lahiri, Shuvendu K. and Wang, Chao}, File = {Bounded synthesis of register transducers - Khalimov2018_Chapter_BoundedSynthesisOfRegisterTran - a - a - c.pdf}, ISBN = {978-3-030-01090-4}, Pages = {494--510}, Publisher = {Springer International Publishing}, Title = {Bounded Synthesis of Register Transducers}, Year = {2018}, date-added = {2020-03-02 14:05:28 +0100}, date-modified = {2020-03-02 14:05:28 +0100}, doi = {10.1007/978-3-030-01090-4_29} }