@article{AkshayBolligGasint:FMSD:2012,
    Author = {Akshay, S. and Bollig, Benedikt and Gastin, Paul},
    File = {Event clock message passing automata a logical characterization and an emptiness checking algorithm - Akshay, Bollig, Gastin (0) (0) - a - a - y.pdf},
    ISSN = {0925-9856},
    Journal = {Formal Methods in System Design},
    Keywords = {timed automata and communicating automata and MSO},
    Language = {English},
    Pages = {1--39},
    Publisher = {Springer US},
    Title = {Event clock message passing automata: a logical characterization and an emptiness checking algorithm},
    URL = {http://dx.doi.org/10.1007/s10703-012-0179-8},
    Year = {2012},
    bdsk-url-1 = {http://dx.doi.org/10.1007/s10703-012-0179-8},
    date-added = {2013-02-22 10:27:02 +0000},
    date-modified = {2018-03-13 08:45:14 +0000},
    doi = {10.1007/s10703-012-0179-8}
}

@article{AkshayBolligGasint:FMSD:2012, Author = {Akshay, S. and Bollig, Benedikt and Gastin, Paul}, File = {Event clock message passing automata a logical characterization and an emptiness checking algorithm - Akshay, Bollig, Gastin (0) (0) - a - a - y.pdf}, ISSN = {0925-9856}, Journal = {Formal Methods in System Design}, Keywords = {timed automata and communicating automata and MSO}, Language = {English}, Pages = {1--39}, Publisher = {Springer US}, Title = {Event clock message passing automata: a logical characterization and an emptiness checking algorithm}, URL = {http://dx.doi.org/10.1007/s10703-012-0179-8}, Year = {2012}, bdsk-url-1 = {http://dx.doi.org/10.1007/s10703-012-0179-8}, date-added = {2013-02-22 10:27:02 +0000}, date-modified = {2018-03-13 08:45:14 +0000}, doi = {10.1007/s10703-012-0179-8} }