@inproceedings{1319629,
    Author = {Aziz Abdulla, Parosh and Deneux, J. and Mahata, P.},
    BookTitle = {Logic in Computer Science, 2004. Proceedings of the 19th Annual IEEE Symposium on},
    File = {Multi-clock timed networks - Aziz Abdulla, Deneux, Mahata (0) (0) - a - a - h.pdf},
    ISSN = {1043-6871},
    Keywords = {discrete time domain; finite state process; multi-clock timed networks; parameterized systems; real-valued clock; safety properties verification; timed processes; clocks; decidability; finite state machines; formal verification;},
    Month = {july},
    Pages = {345 - 354},
    Title = {Multi-clock timed networks},
    Year = {2004},
    bdsk-url-1 = {http://dx.doi.org/10.1109/LICS.2004.1319629},
    date-added = {2012-12-18 13:13:29 +0000},
    date-modified = {2013-11-14 17:41:10 +0000},
    file-2 = {Multi-clock timed networks - Aziz Abdulla, Deneux, Mahata (1) (0) - a - a - h.pdf},
    doi = {10.1109/LICS.2004.1319629}
}

@inproceedings{1319629, Author = {Aziz Abdulla, Parosh and Deneux, J. and Mahata, P.}, BookTitle = {Logic in Computer Science, 2004. Proceedings of the 19th Annual IEEE Symposium on}, File = {Multi-clock timed networks - Aziz Abdulla, Deneux, Mahata (0) (0) - a - a - h.pdf}, ISSN = {1043-6871}, Keywords = {discrete time domain; finite state process; multi-clock timed networks; parameterized systems; real-valued clock; safety properties verification; timed processes; clocks; decidability; finite state machines; formal verification;}, Month = {july}, Pages = {345 - 354}, Title = {Multi-clock timed networks}, Year = {2004}, bdsk-url-1 = {http://dx.doi.org/10.1109/LICS.2004.1319629}, date-added = {2012-12-18 13:13:29 +0000}, date-modified = {2013-11-14 17:41:10 +0000}, file-2 = {Multi-clock timed networks - Aziz Abdulla, Deneux, Mahata (1) (0) - a - a - h.pdf}, doi = {10.1109/LICS.2004.1319629} }